Demonstration of $p-\text{type}$ GaN FinFETs on Silicon Substrates with Ultrahigh Current ON/OFF Ratio of 109 and Reduced Interface Trap Density
Author:
Affiliation:
1. School of Microelectronics, Xidian University,Xi'an,China,710071
2. Guangzhou Institute of Technology, Xidian University,Guangzhou,China,510555
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10102927/10102928/10103032.pdf?arnumber=10103032
Reference14 articles.
1. An Experimental Demonstration of GaN CMOS Technology
2. p-Channel GaN Transistor Based on p-GaN/AlGaN/GaN on Si
3. Self-Aligned E-Mode GaN p-Channel FinFET With ION > 100 mA/mm and ION/IOFF > 10⁷
4. Fabrication of p-channel heterostructure field effect transistors with polarization-induced two-dimensional hole gases at metal–polar GaN/AlInGaN interfaces
5. Gallium nitride-based complementary logic integrated circuits
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