Operation Scheme Optimization for Charge Trap Transistors (CTTs) Based on Fully Depleted Silicon-On-Insulator (FDSOI) Platform-Reference-Cited by-同舟云学术

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Operation Scheme Optimization for Charge Trap Transistors (CTTs) Based on Fully Depleted Silicon-On-Insulator (FDSOI) Platform

Published:2023-03-07 Issue: Volume: Page:
ISSN:
Container-title:2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
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Author:

Wang Wannian¹,Chen Bing¹,Zhao Jiayi¹,Loubriat Sebastien²,Besnard Guillaume³,Maleville Christophe³,Weber Olivier⁴,Cheng Ran¹

Affiliation:

1. School of Micro-Nano Electronics, Zhejiang University,Hangzhou,China

2. CEA-LETI, MINATEC,Grenoble Cedex 9,France,F-38054

3. SOITEC, Parc Technologique des Fontaines,Bernin,France,38190

4. STMicroelectronics,Crolles,France,38926

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10102927/10102928/10103101.pdf?arnumber=10103101

Reference10 articles.

1. High-Source–Drain Voltage-Induced Reliability Issues of Sub-28-nm Node MOSFET’s Application in Resistive-Type Nonvolatile Memory Array

2. Enabling UTBB Strained SOI Platform for Co-Integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-Like Device Architecture

3. A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs

4. 80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

5. Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications

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