System-level Performance of Mos2Synaptic Transistors in MLP and DNN Architectures
Author:
Affiliation:
1. Indian Institute of Technology (IIT) Hyderabad,Electrical Engineering,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10102927/10102928/10103053.pdf?arnumber=10103053
Reference7 articles.
1. DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training;peng;IEEE Trans on CAD of IC,2020
2. Li‐Ion Synaptic Transistor for Low Power Analog Computing
3. The Game Is Not over Yet—Go in the Post-AlphaGo Era
4. Resistive memory device requirements for a neural algorithm accelerator;sapan;IJCNN,2016
5. Emulating synaptic response in n- and p-channel MoS2 transistors by utilizing charge trapping dynamics
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