67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process-Reference-Cited by-同舟云学术

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67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process

Published:2021-05 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Wang Chua-Chin,Kuo Chien-Ping

Funder

Ministry of Science and Technology

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9401028/9401051/09401099.pdf?arnumber=9401099

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

3. Schmitt-Trigger-Based Low Power SRAM Implemented Using 45-nm CMOS Technology;2023 IEEE Region 10 Symposium (TENSYMP);2023-09-06

4. Magnetic Memory Effect in Planar Ferromagnet/Superconductor/Ferromagnet Microbridges Based on Highly Diluted PdFe Alloy;JETP Letters;2022-07

5. Scalable memory elements based on rectangular SIsFS junctions;Journal of Applied Physics;2021-11-07

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