A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration
Author:
Affiliation:
1. Fudan University,State Key Laboratory of ASIC & System, dept. Microelectronics,Shanghai,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9859262/9859267/09859478.pdf?arnumber=9859478
Reference10 articles.
1. Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation
2. A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier
3. A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique
4. A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
5. A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. The Fully Differential Ring Amplifier with Wide Output Voltage Range Using Correlated Level Shifting Technique for The Pipelined ADCs;2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2024-07-02
2. A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity;IEICE Electronics Express;2024
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