A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications
Author:
Affiliation:
1. Hanyang University,Department of Nanoscale Semiconductor Engineering,Seoul,Korea
2. Hanyang University,Department of Electronic Engineering,Seoul,Korea
Funder
Samsung
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9859262/9859267/09859487.pdf?arnumber=9859487
Reference9 articles.
1. Co-Design and Demonstration of a 25-Gb/s Silicon-Photonic Mach–Zehnder Modulator With a CMOS-Based High-Swing Driver
2. A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS
3. A High Efficiency 39GHz CMOS Cascode Power Amplifier for 5G Applications
4. 106 Gb/s PAM-4 Transmitter With 2.1 Vppd Swing in 7nm FinFET Process
5. Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data
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1. A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06
2. 6.8 A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing $\mathbf{3+1}$ Hybrid FFE Taps in 40nm;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19
3. THE EYE OPENING IMPROVEMENT METHOD FOR A HIGH SPEED CURRENT MODE LOGIC DRIVER;Proceedings;2023
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