A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows-Reference-Cited by-同舟云学术

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A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows

Published:2022-08-07 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)
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Author:

Pechmann Stefan¹,Hagelauer Amelie²

Affiliation:

1. Technical University of Munich,Chair of Micro- and Nanosystems Technology,Munich,Germany

2. Fraunhofer EMFT Research Institution for Microsystems and Solid State Technologies,Munich,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9859262/9859267/09859436.pdf?arnumber=9859436

Reference5 articles.

1. A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

2. Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications

3. Multilevel HfO2-based RRAM devices for low-power neuromorphic networks

4. Ratio-based multi-level resistive memory cells;lastras-montaño;Scientific Reports,2021

5. Overview of Resistive Random Access Memory (RRAM): Materials, Filament Mechanisms, Performance Optimization, and Prospects

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

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