Design of High Noise Tolerant Single-Bit Line 8T SRAM Cell
Author:
Affiliation:
1. Madanapalle Institute of Technology & Science,Dept. of ECE,Madanapalle,India
2. Vellore Institute of Technology,School of Electronics Engineering,Chennai,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10169132/10169913/10170595.pdf?arnumber=10170595
Reference15 articles.
1. Variation resilient subthreshold SRAM cell design technique
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3. Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region
4. Single-ended 6T SRAM cell to improve dynamic power dissipation by decreasing activity factor;islam;The Mediterranean Journal of Electronics and Communication,2011
5. Comparative Analysis of Various 9T SRAMCell at 22-nm Technology Node;roy;Proc 2nd IEEE Int Conf on Recent Trends inInformation Systems (ReTIS-15),0
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