An 82–107.6-GHz Integer-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula> ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta

An 82–107.6-GHz Integer- $N$ ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma TDC

Published:2019-02 Issue:2 Volume:54 Page:358-367
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Huang Zhiqiang^ORCID,Luong Howard C.^ORCID

Funder

Hong Kong General Research Funding

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8629373/08526534.pdf?arnumber=8526534

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 45-fs_rms-Jitter, 144-to-162-GHz D-Band Frequency Synthesizer Using a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16

2. A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler;IEICE Electronics Express;2024-01-25

3. Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

4. A 76–82 GHz VCO in 65 nm CMOS With 189.3 dBc/Hz PN FOM and −0.6 dBm Harmonic Power for mm-Wave FMCW Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01

5. A broadband ECL static frequency divider in InP DHBT using differential ft-doubler;IEICE ELECTRON EXPR;2023