Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile
Author:
Affiliation:
1. Vellore Institute of Technology,ICDT Lab, School of Electronics Engineering,Chennai,India,600127
2. National Institute of Technology,iCAS Lab,Department of ECE,Arunachal Pradesh,India,791113
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10483275/10483296/10483492.pdf?arnumber=10483492
Reference22 articles.
1. Model and analysis for combined package and on-chip power grid simulation
2. Synchronous chip-to-chip communication with a multi-chip resonator clock distribution network *
3. Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges
4. Pattern Generation and Estimation for Power Supply Noise Analysis
5. Power Supply Noise in SoCs: Metrics, Management, and Measurement
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