A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers-Reference-Cited by-同舟云学术

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A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

Published:2015-10 Issue:10 Volume:50 Page:2331-2341
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lim Yong,Flynn Michael P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7279217/07167727.pdf?arnumber=7167727

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3. The Fully Differential Ring Amplifier with Wide Output Voltage Range Using Correlated Level Shifting Technique for The Pipelined ADCs;2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2024-07-02

4. The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

5. A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS;Microelectronics Journal;2024-04

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