An Inductorless 20-Gb/s CDR With High Jitter Tolerance
Author:
Funder
Realtek Semiconductor
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8847474/08794621.pdf?arnumber=8794621
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 10-Gb/s 275-fsec Jitter Cryo-CMOS Charge-Sampling CDR for Quantum Computing Application;IEEE Microwave and Wireless Technology Letters;2023-06
2. A 56-GHz Fractional-N PLL With 110-fs Jitter;IEEE Journal of Solid-State Circuits;2023-01
3. SSCS Circuit Analysis and Design Contest: The Winners of the 2022 Edition [Society News];IEEE Solid-State Circuits Magazine;2023
4. A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS;2022 IEEE Asian Solid-State Circuits Conference (A-SSCC);2022-11-06
5. A Closed-Form Transfer Function for Sample and Hold Master Slave Sampling Filter;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-07
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