A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance-Reference-Cited by-同舟云学术

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Published:2019-10 Issue:10 Volume:54 Page:2786-2801
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Bailey Steven^ORCID,Rigge Paul^ORCID,Han Jaeduk^ORCID,Lin Richard,Chang Eric Y.^ORCID,Mao Howard,Wang Zhongkai,Markley Chick,Izraelevitz Adam M.,Wang Angie,Narevsky Nathan,Bae Woorham^ORCID,Shauck Steve,Montano Sergio,Norsworthy Justin^ORCID,Razzaque Munir^ORCID,Ma Wen Hau,Lentiro Akalu,Doerflein Matthew^ORCID,Heckendorn Darin,McGrath Jim,DeSeta Franco,Shoham Ronen,Stellfox Mike,Snowden Mark,Cole Joseph,Fuhrman Daniel R.,Richards Brian^ORCID,Bachrach Jonathan^ORCID,Alon Elad,Nikolic Borivoje^ORCID

Funder

Defense Advanced Research Projects Agency

Berkeley Wireless Research Center

Berkeley Agile Design of Efficient Processing Technologies (ADEPT) lab

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8847474/08765410.pdf?arnumber=8765410

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