A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking-Reference-Cited by-同舟云学术

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Published:2019-01 Issue:1 Volume:54 Page:197-209
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Young-Ju^ORCID,Kwon Hye-Jung,Doo Su-Yeon,Ahn Minsu,Kim Yong-Hun,Lee Yong-Jae,Kang Dong-Seok,Do Sung-Geun,Lee Chang-Yong,Cho Gun-Hee,Park Jae-Koo,Kim Jae-Sung,Park Kyungbae,Oh Seunghoon,Lee Sang-Yong,Yu Ji-Hak,Yu Kihun^ORCID,Jeon Chulhee,Kim Sang-Sun,Park Hyun-Soo,Lee Jeong-Woo^ORCID,Cho Seung-Hyun,Park Keon-Woo,Kim Yongjun,Seo Young-Hun,Shin Chang-Ho,Lee Chan-Yong,Bang Sam-Young,Park Younsik,Choi Seouk-Kyu,Kim Byung-Cheol,Han Gong-Heum,Bae Seung-Jun,Kwon Hyuk-Jun,Choi Jung-Hwan,Sohn Young-Soo,Park Kwang-Il,Jang Seong-Jin,Jin Gyoyoung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8613098/08588344.pdf?arnumber=8588344

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