Current Reference Pre-Charging Techniques for Low-Power Zero-Crossing Pipeline-SAR ADCs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/6756988/06729096.pdf?arnumber=6729096
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1. An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
2. Comparative Study of High Speed ADCs;Highlights in Science, Engineering and Technology;2022-12-27
3. A dual-residue pipelined SAR ADC using only zero-crossing signals;Analog Integrated Circuits and Signal Processing;2021-05-03
4. A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm;IEEE Journal of Solid-State Circuits;2021-04
5. A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-09
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