0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance-Reference-Cited by-同舟云学术

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0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance

Published:2014-07 Issue:7 Volume:49 Page:1487-1498
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Do Anh Tuan,Yin Chun,Velayudhan Kavitha,Lee Zhao Chuan,Yeo Kiat Seng,Kim Tony Tae-Hyoung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6841653/06805234.pdf?arnumber=6805234

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low power content addressable memory designing and implementation using voltage swing self adjustable match line technique;Sustainable Computing: Informatics and Systems;2024-09

2. Ferroelectric Devices for Content-Addressable Memory;Nanomaterials;2022-12-19

3. A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge;IEEE Journal of Solid-State Circuits;2021-08

4. A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

5. Design and Analysis of LFSR based Content Addressable Memory;2021 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS);2021-02-19

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