A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization-Reference-Cited by-同舟云学术

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A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

Published:2013-08 Issue:8 Volume:48 Page:1818-1828
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Jiangfeng Wu ,Chun-Ying Chen ,Tianwei Li ,Lin He ,Wenbo Liu ,Wei-Ta Shih ,Tsai Shauhyuarn Sean,Binning Chen ,Chun-Sheng Huang ,Hung Bryan Juo-Jung,Hung Hing T.,Jaffe Steven,Loke Kun Tan ,Hung Vu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6564404/06515198.pdf?arnumber=6515198

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

2. A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer;IEICE Electronics Express;2023-12-10

3. A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique;Electronics;2022-11-30

4. Estimation of Broadband Time-Interleaved ADC’s Impairments and Performance Using Only Single-Tone Measurements;IEEE Access;2022

5. A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2021

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