A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8118328/08068949.pdf?arnumber=8068949
Cited by 38 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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5. A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with One-Tap DFE and Time-Interpolation;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
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