A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration-Reference-Cited by-同舟云学术

A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration

Published:2023-12 Issue:12 Volume:70 Page:4679-4691
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wei Lai¹^ORCID,Zheng Zihao¹,Markulic Nereo²^ORCID,Lagos Jorge²^ORCID,Martens Ewout²^ORCID,Martins Rui Paulo¹^ORCID,Zhu Yan¹,Craninckx Jan²^ORCID,Chan Chi-Hang¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Faculty of Science and Technology, State Key Laboratory of Analog and Mixed Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China

2. Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium

Funder

National Natural Science Foundation of China

Macau FDCT File

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10363413/10225439.pdf?arnumber=10225439

Reference30 articles.

1. A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion

2. A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

3. An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion

4. A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

5. A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS

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