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i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs

  • Published:2020-12 Issue:12 Volume:67 Page:4651-4659
  • ISSN:1549-8328
  • Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Jaiswal AkhileshORCID,Agrawal AmoghORCID,Ali Mustafa F.ORCID,Sharmin SaimaORCID,Roy KaushikORCID

Funder

C-BRIC, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) Program

DARPA

National Science Foundation, Intel Corporation

Vannevar Bush Faculty Fellowship

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Aging and Process Variability on SRAM-Based In-Memory Computing Architectures;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06

2. In-Memory Encryption using XOR-based Feistel Cipher in SRAM Array;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

4. A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC;Microelectronics Journal;2024-03

5. A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18
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