A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell
Author:
Affiliation:
1. MNIT,Jaipur
2. NFSU,Gandhinagar
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10467041/10466793/10466805.pdf?arnumber=10466805
Reference23 articles.
1. Technology and Modeling of Nonclassical Transistor Devices
2. Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/ RF applications
3. Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field
4. Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs
5. A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
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