A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

Author:

Lakshmi VijayaORCID,Reuben JohnORCID,Pudi VikramkumarORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Enhanced FPGA linear phase FIR filter with amalgam multiplier;International Journal of Electronics;2024-05-10

2. Design and Analysis of Majority Logic-Based Approximate 5:2 Compressors and Multipliers;2024 5th International Conference on Computer Engineering and Application (ICCEA);2024-04-12

3. In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-03

4. A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology;Proceedings of the 2023 International Conference on Electronics, Computers and Communication Technology;2023-11-17

5. Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption;Integration;2023-11

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