Verification of processor microarchitectures-Reference-Cited by-同舟云学术

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Verification of processor microarchitectures

Published: Issue: Volume: Page:
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Container-title:Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)
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Author:

Shen J.,Abraham J.A.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/6209/16582/00766664.pdf?arnumber=766664

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM);2022 IEEE 12th International Conference on Control System, Computing and Engineering (ICCSCE);2022-10-21

2. Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-02

3. Verification of Ethernet IP Core MAC Design Using Deterministic Test Methodology;2008 IEEE Instrumentation and Measurement Technology Conference;2008-05

4. Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture;26th IEEE VLSI Test Symposium (vts 2008);2008-04

5. Software-based self-testing of microprocessors;Journal of Systems Architecture;2006-05

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