Instruction Extension of RV32I and GCC Back End for Ascon Lightweight Cryptography Algorithm

Author:

Altinay Ozlem,Ors Berna

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Implementation of CRYSTALS-Kyber Post-Quantum Algorithm Using RISC-V Processor;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

2. Smartphone Security and Privacy: A Survey on APTs, Sensor-Based Attacks, Side-Channel Attacks, Google Play Attacks, and Defenses;Technologies;2023-06-12

3. RISC-V ISA Extension Toolchain Supports: A Survey;Proceedings of the 2023 4th International Conference on Computing, Networks and Internet of Things;2023-05-26

4. Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA;Future Internet;2023-05-19

5. RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures;Electronics;2022-09-21

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