A systolic architecture for modulo multiplication
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx4/82/10018/00475251.pdf?arnumber=475251
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low-Complexity High-Radix RNS Multiplier;IEEE Transactions on Circuits and Systems I: Regular Papers;2009-11
2. Low-complexity polynomials modulo integer with linearly incremented variable;2008 IEEE Workshop on Signal Processing Systems;2008-10
3. ON THE DESIGN OF EFFICIENT MODULAR ADDERS;Journal of Circuits, Systems and Computers;2005-10
4. A Novel Architecture and a Systematic Graph-Based Optimization Methodology for Modulo Multiplication;IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications;2004-02
5. A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n - (2p 1));The Computer Journal;2004-01-01
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