ON THE DESIGN OF EFFICIENT MODULAR ADDERS-Reference-Cited by-同舟云学术

ON THE DESIGN OF EFFICIENT MODULAR ADDERS

Published:2005-10 Issue:05 Volume:14 Page:965-972
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

VERGOS HARIDIMOS T.¹,EFSTATHIOU CONSTANTINOS²

Affiliation:

1. Computer Engineering and Informatics Department, University of Patras, 26 500, Greece

2. Informatics Department, TEI of Athens, 12 210, Greece

Abstract

Modular adders are met in various applications of computer systems. In this paper, we investigate a new architecture for their design that utilizes a carry save adder stage and two binary adders that operate in parallel. Realizations in static CMOS reveal that the introduced architecture leads to modular adder implementations that offer significant savings in delay and power consumption over implementations based on previously proposed architectures. In parallel, the proposed architecture offers significantly smaller implementation area for small operand widths.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126605002726

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