Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops

Author:

Kamei Aika1,Kojima Takuya1,Amano Hideharu1,Yokoyama Daiki2,Miyauchi Hisato2,Usami Kimiyoshi2,Hiraga Keizo3,Suzuki Kenta3,Bessho Kazuhiro3

Affiliation:

1. Keio University,Yokohama,Japan

2. Shibaura Institute of Technology,Tokyo,Japan

3. Sony Semiconductor Solutions Corporation,Atsugi,Japan

Publisher

IEEE

Reference19 articles.

1. Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

2. PipeRench: A virtualized programmable datapath in 0.18 micron technology

3. Kilocore: Scalable, High Performance and Power Efficient Coarse Grained Reconfigurable Fabrics;levine;Proc of International Sym-posium on Advanced Reconfigurable Systems,0

4. S5: the architecture and development flow of a software configurable processor

5. EGRA: A Coarse Grained Reconfigurable Architectural Template

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1. A Survey of Emerging Memory in a Microcontroller Unit;Micromachines;2024-04-01

2. Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

3. Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems;IEICE Transactions on Electronics;2023-07-01

4. A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04

5. Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges;2022 International Conference on Field-Programmable Technology (ICFPT);2022-12-05

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