Simulation challenges of warpage for wafer- and panel level packaging
Author:
Affiliation:
1. Fraunhofer Institute for Reliability and Microintegration (IZM),Berlin,Germany
2. Technische Universität Berlin,Research Center of Microperipheric Technologies,Berlin,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9146595/9152196/09152797.pdf?arnumber=9152797
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. How to Manipulate Warpage in Fan-out Wafer and Panel Level Packaging;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
2. Development and Demonstration on Process-Oriented Warpage Simulation Methodology of Fan-Out Panel-Level Package in Multilevel Integration;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-12
3. Combining Process Modeling and Machine Learning Technology to Predict the Warpage of the Panel-Level Packaging After Debonding;2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT);2023-10-25
4. Experimental and simulative study of warpage behavior for fan-out wafer-level packaging;Microelectronics Reliability;2022-08
5. Manufacturing for Reliability of Panel-Level Fan-out Packages;Reliability of Organic Compounds in Microelectronics and Optoelectronics;2022
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