Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator-Reference-Cited by-同舟云学术

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Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator

Published:2020-06 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE Symposium on VLSI Circuits
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Author:

Kim Sung-Jin,Myers Zachary,Herbst Steven,Lim ByongChan,Horowitz Mark

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9146894/9162771/09162800.pdf?arnumber=9162800

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm² Active Area in 12nm FinFET;2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits);2024-06-16

2. RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

3. CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

4. A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

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