A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling-Reference-Cited by-同舟云学术

A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling

Published:2022-07-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 59th ACM/IEEE Design Automation Conference
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Author:

Zhang Qiaochu¹,Su Shiyu¹,Chen Mike Shuo-Wei¹

Affiliation:

1. University of Southern California

Funder

Defense Advanced Research Projects Agency

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3489517.3530502

Reference12 articles.

1. Stochastic analog-to-digital conversion

2. Zhengyu Chen , Hai Zhou , and Jie Gu . 2019 . Digital Compatible Synthesis , Placement and Implementation of Mixed-Signal Time-Domain Computing. In 2019 56th ACM/IEEE Design Automation Conference (DAC). IEEE, 1--6. Zhengyu Chen, Hai Zhou, and Jie Gu. 2019. Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. In 2019 56th ACM/IEEE Design Automation Conference (DAC). IEEE, 1--6.

3. A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS

4. A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

5. An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells

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