An efficient postprocessor architecture for channel mismatch correction of time interleaved ADCs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5497864/5506939/05507040.pdf?arnumber=5507040
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-09
2. A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28
3. Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC;Analog Integrated Circuits and Signal Processing;2019-03-22
4. Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing;Cognitive Radio;2017-07-05
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