A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations-Reference-Cited by-同舟云学术

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

Published:2022-09 Issue:9 Volume:69 Page:3645-3649
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Be Gabriele¹^ORCID,Parisi Angelo¹^ORCID,Bertulessi Luca¹^ORCID,Ricci Luca¹,Scaletti Lorenzo¹^ORCID,Mercandelli Mario¹^ORCID,Lacaita Andrea L.¹^ORCID,Levantino Salvatore¹^ORCID,Samori Carlo¹^ORCID,Bonfanti Andrea¹^ORCID

Affiliation:

1. Department of Electronics, Information, and Bioengineering, Politecnico di Milano, Milan, Italy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9869776/09793854.pdf?arnumber=9793854

Reference24 articles.

1. A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

2. 22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS

3. A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs;jin;IEEE Trans Circuits Syst II Analog Digit Signal Process,2000

4. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration

5. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

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