Stacked PMOS clamps for high voltage power supply protection
Author:
Publisher
ESD Assoc
Link
http://xplorestaging.ieee.org/ielx5/6641/17711/00818992.pdf?arnumber=818992
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1. Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
2. A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology;2022 IEEE International Reliability Physics Symposium (IRPS);2022-03
3. Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp;ACM Transactions on Design Automation of Electronic Systems;2016-07-26
4. High Area-Efficient ESD Clamp Circuit With Equivalent $RC$-Based Detection Mechanism in a 65-nm CMOS Process;IEEE Transactions on Electron Devices;2013-03
5. ESD design challenges in state-of-the-art analog technologies;Microelectronics Reliability;2012-09
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