A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology
Author:
Affiliation:
1. University of Illinois at Urbana-Champaign,Department of Electrical and Computer Engineering,Urbana,IL,USA,61801
2. Analog Devices, Inc,Wilmington,MA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764514.pdf?arnumber=9764514
Reference9 articles.
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3. Stacked PMOS clamps for high voltage power supply protection;maloney;Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396),1999
4. A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process
5. A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies
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