On the scaling limit of ultrathin SOI MOSFETs-Reference-Cited by-同舟云学术

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On the scaling limit of ultrathin SOI MOSFETs

Published:2006-05 Issue:5 Volume:53 Page:1137-1141
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Wei-Yuan Lu ,Yuan Taur

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/34109/01624695.pdf?arnumber=1624695

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis on the impact of interface Trap distributions on SOI DMG FinFETs: Overlap/underlap configurations;Micro and Nanostructures;2024-01

2. Efficient RF Small-Signal Parasitic Parameters Extraction Technique For The Advanced MOSFETs;2023 2nd International Conference on Electronics, Energy and Measurement (IC2EM);2023-11-28

3. Two-dimensional analytical model for fully depleted SOI MOSFETs with vertical trapezoid doping including effects of the interface trapped charges;Japanese Journal of Applied Physics;2023-11-24

4. Performance analysis of dielectric modulated underlap FD-SOI MOSFET for biomolecules detection;Applied Physics A;2022-11-22

5. Performance Upper Limit of Sub-10 nm Monolayer MoS₂ Transistors with MoS₂–Mo Electrodes;The Journal of Physical Chemistry C;2022-07-15

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