Design of Ultra-Low Power Comparator in 65 NM CMOS Technology with Rail-to-Rail Input Range-Reference-Cited by-同舟云学术

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Design of Ultra-Low Power Comparator in 65 NM CMOS Technology with Rail-to-Rail Input Range

Published:2023-09-20 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE AFRICON
language:
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Author:

Nagy Lukas¹,Sovcik Michal¹,Stopjakova Viera¹

Affiliation:

1. Institute of Electronics and Photonics, Slovak University of Technology,Bratislava,Slovakia

Funder

Slovak Research and Development Agency

Ministry of Education, Science, Research

Electronic Components and Systems for European Leadership Joint Undertaking

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10293181/10293212/10293614.pdf?arnumber=10293614

Reference10 articles.

1. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

2. Rail-to-Rail Dynamic Voltage Comparator Scalable Down to pW-Range Power and 0.15-V Supply

3. EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method

4. Design of a Low-Power Ultra High Speed Dynamic Latched Comparator in 90-nm CMOS Technology

5. GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

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