Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM-Reference-Cited by-同舟云学术

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Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM

Published:1997 Issue: Volume: Page:
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Container-title:Symposium on VLSI Technology
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Author:

Itabashi ,Tsuboi ,Nakamura ,Hashimoto ,Futoh ,Fukuda ,Hanyu ,Asai ,Chijimatsu ,Kawamura ,Yao ,Takagi ,Ohta ,Karasawa ,Iio ,Onods ,Inoue ,Nomura ,Satoh ,Higashimoto ,Matsumiya ,Miyabo ,Ikeda ,Yamazaki ,Miyajima ,Watanabe ,Kawamura ,Taguchi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/4913/13565/00623675.pdf?arnumber=623675

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. CD control in phase-edge lithography: the effects of lens aberration and pattern layout;SPIE Proceedings;2002-07-15

4. Novel Borderless Metal Contact Process Using a Self-Stopping Layer for a 4Gb DRAM and beyond;Journal of the Korean Physical Society;2002-04-01

5. Patterning of random interconnect using double exposure of strong-type PSMs;SPIE Proceedings;2001-09-14

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