A 1.28 &mu;m<sup>2</sup> bit-line shielded memory cell technology for 64 Mb DRAMs-Reference-Cited by-同舟云学术

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A 1.28 &mu;m² bit-line shielded memory cell technology for 64 Mb DRAMs

Published:1990 Issue: Volume: Page:
ISSN:
Container-title:Digest of Technical Papers.1990 Symposium on VLSI Technology
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Author:

Kawamoto Y.,Kaga T.,Nishida T.,Iijima S.,Kure T.,Murai F.,Kisu T.,Hisamoto D.,Shinriki H.,Nakagome Y.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx2/147/3344/05727444.pdf?arnumber=5727444

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimization of process conditions for the formation of hemispherical-grained (HSG) silicon in high-density DRAM capacitor;Materials Science in Semiconductor Processing;2002-12

2. Microstructure evolution of nanometer-sized hemispherical-grained Si deposited by RTCVD;Materials Science and Engineering: C;2001-08

3. Investigation on Leakage Current Reduction of Photo‐CVD Tantalum Oxide Films Accomplished by Active Oxygen Annealing;Journal of The Electrochemical Society;1992-01-01

4. Compact sources in Japan and their intended applications (invited);Review of Scientific Instruments;1992-01

5. Oxide‐nitride storage dielectrics on smooth and rough polycrystalline silicon layers;Applied Physics Letters;1991-07-15

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