A 22.5–27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter-Reference-Cited by-同舟云学术

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A 22.5–27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter

Published:2019-09 Issue:9 Volume:2 Page:111-114
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Tsai Cheng-Hsueh^ORCID,Pepe Federico^ORCID,Mangraviti Giovanni^ORCID,Zong Zhiwei,Craninckx Jan^ORCID,Wambacq Piet

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/8871355/08878209.pdf?arnumber=8878209

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024

2. Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs;IEEE Journal of Solid-State Circuits;2024-01

3. Throughput enhancement for millimeter wave communications using reconfigurable intelligent surfaces;Telecommunication Systems;2022-01-07

4. A 22.7‐ to 44.2‐GHz Darlington dual‐injection injection‐locked frequency tripler with >35dBc harmonic rejection for multiband 5G communication systems;International Journal of Circuit Theory and Applications;2021-12-28

5. A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS;2021 IEEE Asian Solid-State Circuits Conference (A-SSCC);2021-11-07

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