A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage–Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8011414/8871355/08758830.pdf?arnumber=8758830
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW;IEEE Journal of Solid-State Circuits;2023-04
2. A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration;IEICE Electronics Express;2023-02-10
3. A 1.9-ps 8x Phase Interpolation TDC for Time-based Analog-to- Digital Converter with Capacitance Compensation Self-Calibration;IEICE ELECTRON EXPR;2023
4. A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology;Analog Integrated Circuits and Signal Processing;2022-06-21
5. Radio frequency analog-to-digital converters: Systems and circuits review;Microelectronics Journal;2022-01
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