A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology-Reference-Cited by-同舟云学术

A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology

Published:2022-06-21 Issue:3 Volume:112 Page:467-473
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Fani Seyed Hamid,Rahiminejad Ehsan^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s10470-022-02063-6.pdf

Reference17 articles.

1. Ohhata, K. (2019). A 2.3-mW, 1-GHz, 8-bit fully time-based two-step ADC using a high-linearity dynamic VTC. IEEE Journal of Solid-State Circuits, 54(7), 2038–2048.

2. Chen, L. J., & Liu, S. I. (2016). A 10-bit 40-ms/s time-domain two-step adc with short calibration time. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(2), 126–130.

3. Ohhata, K. (2018). Low-power, high-speed time-based subranging ADCs. In IEEE International Symposium on Intelligent Signal Processing and Communications System (ISPACS), (pp. 463–468).

4. Narasimman, N., & Kim, T. T. (2016). An ultra-low voltage, VCO-based ADC with digital background calibration. In IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1458–1461).

5. Xing, X., & Gielen, G. (2015). A 42 fJ/step-FoM two-step VCO-based delta-sigma ADC in 40 nm CMOS. IEEE Journal of Solid-State Circuits, 50(3), 714–723.

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