Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High MemoryWindow in FEFETs for NAND Applications-Reference-Cited by-同舟云学术

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Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High MemoryWindow in FEFETs for NAND Applications

Published:2024-03-03 Issue: Volume: Page:1-3
ISSN:
Container-title:2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
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Author:

Das Dipjyoti¹,Park Hyeonwoo¹,Wang Zekai¹,Zhang Chengyang¹,Ravindran Prasanna Venkatesan¹,Park Chinsung¹,Afroze Nashrah¹,Hsu Po-Kai¹,Tian Mengkun¹,Chen Hang¹,Chern Winston¹,Lim Suhwan²,Kim Kwangsoo²,Kim Kijoon²,Kim Wanki²,Ha Daewon²,Yu Shimeng¹,Datta Suman¹,Khan Asif¹

Affiliation:

1. Georgia Tech,USA

2. Samsung Electronics Co. Ltd,South Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10511270/10511310/10511400.pdf?arnumber=10511400

Reference11 articles.

1. 3D NAND Scaling in the next decade

2. CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

3. (Invited) 3D-NAND Reliability: Review of key mechanisms and mitigations

4. Reliability of 3D NAND Flash for Future Storage Systems (Invited)

5. First demonstration of ferroelectric Si:HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation;2024 IEEE International Memory Workshop (IMW);2024-05-12

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