Optimization of Tungsten Plug Thin Film Process to Improve the Fill Seam and Contact Resistance in 180nm CMOS Technology-Reference-Cited by-同舟云学术

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Optimization of Tungsten Plug Thin Film Process to Improve the Fill Seam and Contact Resistance in 180nm CMOS Technology

Published:2024-03-03 Issue: Volume: Page:1-3
ISSN:
Container-title:2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
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Author:

Chauhan A.K.¹,Teja V.S.¹,Chawla P.¹,Sharma A.K.¹,Attri R.¹,Gupta M.¹,Singh M.K.¹,Wadhwa M.¹

Affiliation:

1. Semi-Conductor Laboratory,S.A.S Nagar,Punjab,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10511270/10511310/10511484.pdf?arnumber=10511484

Reference11 articles.

1. W nucleation on TiN from WF6 and SiH4

2. Impact of TiN Barrier Layer on Contact Resistance of Tungsten Filled Vias

3. Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

4. Integration of MOCVD titanium nitride with collimated titanium and ion metal plasma titanium for 0.18-μm logic process

5. Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device

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