ReRAM-based Ratioed Combinational Circuit Design: a Solution for in-Memory Computing
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9199028/9200237/09200279.pdf?arnumber=9200279
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Cascade and Extensible In-Memory Arithmetic Computing in 2T1R ReRAM Arrays Using Time-Sum-Logic Design;IEEE Access;2024
2. Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM;2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS);2022-11-16
3. Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03
4. On the Design and Development of a ReRAM-based Computational Memory Prototype;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03
5. Ubiquitous memristors on-chip in multi-level memory, in-memory computing, data converters, clock generation and signal transmission;Metal Oxides for Non-volatile Memory;2022
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