Cascade and Extensible In-Memory Arithmetic Computing in 2T1R ReRAM Arrays Using Time-Sum-Logic Design-Reference-Cited by-同舟云学术

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Cascade and Extensible In-Memory Arithmetic Computing in 2T1R ReRAM Arrays Using Time-Sum-Logic Design

Published:2024 Issue: Volume:12 Page:104081-104090
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Zhu Wei¹^ORCID,He Yi-Xing¹,Li Hao-Nan¹,Liu Xian-Qin¹,Zhang Siwen¹,Wang Lei¹,Zhu Jiang¹,Wang Yue-Qi¹,Zhang Jincheng¹^ORCID,Hao Yue¹^ORCID,Ma Haijiao Harsan¹^ORCID

Affiliation:

1. Low Dimensional Quantum Physics and Device Group, School of Microelectronics, Xidian University, Xi’an, China

Funder

National Key Research and Development Program of China

Fundamental Research Funds for the Central Universities

Interdisciplinary Cultivation Program of Xidian University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/6287639/10380310/10604864.pdf?arnumber=10604864

Reference30 articles.

1. Cramming More Components Onto Integrated Circuits

2. The End of Moore's Law: A New Beginning for Information Technology

3. Memristor-The missing circuit element

4. The missing memristor found

5. Emerging Memristor-Based Logic Circuit Design Approaches: A Review

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