Realization of Turbo Decoder on Coarse Grained Reconfigurable Architectures
Author:
Affiliation:
1. Amrita Vishwa Vidyapeetham,Amrita School of Engineering, Coimbatore,Department of Electronics and Communication Engineering,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10038981/10039721/10040088.pdf?arnumber=10040088
Reference21 articles.
1. Pillars: An Integrated CGRA Design Framework;guo;WOSET,2020
2. VLSI Implementation of Turbo Coder for LTE using Verilog HDL
3. Low Latency Max Log MAP based Turbo Decoder
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2. Turbo Decoding Theory: Derivation and Performance Evaluation;2024 4th Asia-Pacific Conference on Communications Technology and Computer Science (ACCTCS);2024-02-24
3. Implementation of Successive Cancellation Polar Decoder Architecture;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14
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