Low Latency Max Log MAP based Turbo Decoder

Author:

Narayanan Aswathy,Murugan Senthil,Bhakthavatchalu Ramesh

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High Performance and Low Power Axi-Lite 4 Master Controller Using System Verilog;2024 2nd International Conference on Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA);2024-03-15

2. Design of Low-Power Turbo Encoder and Decoder for NB-IoT;Chinese Journal of Electronics;2024-03

3. An FPGA Implementation of Turbo Decoding in VDES;2023 IEEE 5th International Conference on Civil Aviation Safety and Information Technology (ICCASIT);2023-10-11

4. Design of Low-Power Turbo Coder for Low-Energy Mobile Communications;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

5. Realization of Turbo Decoder on Coarse Grained Reconfigurable Architectures;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24

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