Optimization of Ge Gate All Around Field-Effect Transistors at a deca-nm node for Low Power Applications

Author:

Choudhary Sumit1,Mohan Chander2,Chauhan Manvender1,Prasad B.2,Sharma Satinder K.1

Affiliation:

1. Indian Institute of Technology, Mandi,School of Computing and Electrical Engineering,Mandi,India

2. Kurukshetra University,Department of Electronic Science,Kurukshetra,India

Funder

Kurukshetra University

Publisher

IEEE

Reference23 articles.

1. High performance fully-depleted tri-gate CMOS transistors

2. 10nm FINFET technology for low power and high-performance applications A 10nm Platform Technology for Low Power and High-Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI;seo,2014

3. Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

4. Ge GAA FETs and TMD FinFETs for the Applications Beyond Si—A Review

5. Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability;su;Technical Digest - International Electron Devices Meeting IEDM,2018

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