Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing
Author:
Affiliation:
1. KU Leuven
2. imec Leuven
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937962.pdf?arnumber=9937962
Reference8 articles.
1. Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing – A Circuit Blueprint, Device Options and Requirements
2. Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing
3. First demonstration of sub-12 nm Lg gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices;subhechha;IEEE Symposium on VLSI Technology,2021
4. Multi-pillar SOT-MRAM for Accurate Analog in-Memory DNN Inference;doevenspecks;Symposium on VLSI Technology,2021
5. Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration
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