Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8375243/8383743/08383790.pdf?arnumber=8383790
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Single-Event Transient (SET) Tolerant Dynamic Bias Comparator in 65-nm CMOS;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
2. Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect;Electronics;2023-08-03
3. Qualification of a new Total Ionizing Dose Facility Using a Hopewell GR420 Irradiator;2023 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with 2023 NSREC);2023-07
4. Design and Characterization of a Picosecond Timing ASIC in 55-nm CMOS;IEEE Transactions on Nuclear Science;2023-06
5. Design of SEU Tolerant Read Circuit for Non-Volatile Memories with high reliability;2023 5th International Conference on Radiation Effects of Electronic Devices (ICREED);2023-05-24
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